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KB8527B
INTRODUCTION
KB8527B is a monolithic circuit which can be used in high performance 60MHz MCA type CLP System.
1 CHIP CLP SUBSYSTEM IC
48 -QFP- 1010E
The KB8527B is a subsystem IC for FM / FSK receiving systems and a complete one chip FM / FSK receiver IC for 60MHz system. Its feature includes receiving functions for FM / FSK systems, a compandor to remove external noise, and PLL ( Phase Lock Loop ) of channel selection which blocks surrounding frequency interference. The KB8527B can be used with a wide range of FM / FSK VHF bandwidth systems, including cordless phone, and the narrow band voice and data sending / receiving systems. To make applications easily and simply, pheripheral parts are minimized.
ORDERING INFORMATION
Device + KB8527BQ Package 48 - QFP - 1010E Operating Temperature -20oC ~ + 70oC
+ : New product
FEATURES
U
Operating voltage range : 2.0V ~ 5.5V Typical supply current : 13.5mA at 3.6V Built - in low battery detection function ( selectable 3.45V, 3.3V, 3.0V, 2.2V, 2.1V ) Built - in speaker amplifier
U
U
U
* Built - in splatter filter * Built - in dual conversion receiver, compandor and universal PLL
U
FM Receiver - Complete dual coversion circuit - Excellent input sensitivity (0.7Vrms at 20dB SINAD) Compandor - Easy gain control to use external component - Included ALC (Automatic Level Control) circuit - Included Mute logic Universal PLL - RX (TX) divided counter range : 1/16 ~ 1/16383 - Reference frequency divided counter range : 1/16 ~ 1/4095 - Lock detector signal output - Serial interface with MICOM for controlling each block
U
U
KB8527B
BLOCK DIAGRAM
GND(RX) VCC(RX)
1 CHIP CLP SUBSYSTEM IC
DSCO
DSCI
2LOI
2MO
36
35
34
33
32
31
30
29
28
RAO
QCI
LD
27
26
25
X-tal OSC
Limiting IF AMP
FSK COMP
MDO
2LOI
LI
Regulator (1V)
VREF
24
VREF
(COMP)
2MI 37 1MO
2nd MIX
IF AMP (455KHz)
38
Meter Driver Rectifier
PRI + -
23 22
ALC EPI
1LOI 39 1LOI 40
RX VCO
Quad Detector AMP
Carrier Detector
21 ERC SUM AMP 20 EO 19 SAI 18 SAO1 SPK AMP 17 SAO2 16 VCC
(COMP)
VCO 41
RX
1st MIX
IF AMP (10.7MHz)
1MI 42 1MI 43 GND
(PLL)
Low Battery Detector
Gain Cell
SPK AMP
Regulator ( 2.15 V )
Buffer
Limiter
44
SUM AMP
+ PRI
PDR 45 VREF
(PLL)
Programmable Counter ( RX ) Gain Cell Programmable Counter ( TX ) Programmable Counter ( REF )
-
15 GND
(COMP)
14 CPI+ 13 CPI -
46 47
ALC 4_25 CNT Rectifier
VCC
(PLL)
TIF 48
RX Phase Detector
TX Phase Detector
Splatter Filter
fMCU
CONTROL
Compandor mute
1
PDT
2
CO
3
SFI
4
SFO
5
CDO/LDT
6
GND(PLL)
7
CLK
8
DATA
9
EN
10
LBD
11
AGIC
12
CRC
KB8527B
1 CHIP CLP SUBSYSTEM IC
PIN CONFIGURATION
VCC(RX)
GND(RX)
DSCO 26
DSCI
36 2MI 37 1MO 38 1LOI 39 1LOI 40 VCORX 41 1MI 42 1MI 43 GND(PLL) 44 PDR 45 VREF(PLL) 46 VCC(PLL) 47 TIF 48 1 PDT
35 34
33
32
31
QCI
LD
30
29
28 27
25 24 VREF(COMP) 23 ALC 22 EPI 21 ERC 20 EO
KB8527B
MDO 19 SAI 18 SAO1 17 SAO2 16 VCC(COMP) 15 GND (COMP) 14 CPI+ 13 CPI 12 CRC
2LOI
2LOI
2MO
2 CO
3 SFI
4 SFO
5 CDO/LDT
6 GND(PLL)
7 CLK
8 DATA
RAO 9 EN
LI
10 LBD
11 AGIC
KB8527B
PIN DESCRIPTION
Pin No Symbol
1 CHIP CLP SUBSYSTEM IC
Description Phase detector output terminal of the transmitter at PLL.
1
PDT
If fTX > fREF or fTX is leading If fTX < fREF or fTX is lagging if fTX = fREF and the same phase
the output is negative pulse the output is positive Pulse the output is High Impedance
2
CO SFI
Compressor output terminal of compandor ; connected to the splatter filter amp input terminal. Input terminal of Splatter filter amp. Output terminal of Splatter filter amp.
3 4
SFO
LDT : Output terminal of transmitter lock detector in PLL block. Output is low if PLL is in lock state and is high if PLL is in unlock state. LDT/ CDO CDO : As an output terminal of the carrier detector buffer, connected to (RSSI ) terminal of MICOM. This pin outputs the contents of Meter Driver buffer which is turned on / off, according to the signal level detected by Meter Driver. Ground. Ground of logic section at PLL.
5
6
GNDPLL
7 8 9
CLK DATA EN
These pins are serial interface terminals for programming reference counter, auxiliary reference counter, TX channel counter, RX channel counter and control block that controls internal each block with test mode and power saving mode.
10
LBD
Low Battery Detecting output. ( Selectable 3.45V, 3.3V, 3.0V, 2.2V, 2.0V ). During the normal operation, output level is low, but it is high at low battery detection. As this pin is an open collector type, it requires a pull - up resister.
This pin bypasses AC elements at the feedback loop which come from the SUM 11 AGIC amp block of COMPRESSOR. A capacitor should be connected between this terminal and GND. ( C = 2.2 uF )
KB8527B
Pin No 12 Symbol CRC
1 CHIP CLP SUBSYSTEM IC
Description Converts waveform from the full wave rectifier to DC element at the rectifier block of Compressor. ( RC = 33 msec ) Pre - amp inverting input terminal of Compressor. Adjusts the negative feedback loop gain. ( in application, gain is 5 ) Pre - amp non - inverting input terminal of Compressor. Used as an input terminal for voice signals.
13
CPI -
14
CPI +
15
GND
(COMP)
Ground. Ground of Compandor. Supply voltage. Power supply terminal of Compandor.
16
Vcc
(COMP)
Output terminal of speaker amp 2. 17 SAO 2 This signal is the same as SAO1 output, but phase difference is 180o DC voltage level is ( Vcc - 0.7V ) / 2. Output terminal of Speaker amp 1. DC voltage level is ( Vcc - 0.7V ) / 2. for SAO1.
18
SAO 1
19
SAI
Speaker Amp 1 input terminal. Between this terminal and Expander output terminal, uses a AC coupled.
20
EO
Output terminal of Expander, from which a regenerated voice signals are emitted. Converts waveform from the full wave rectifier to DC element at the rectifier block
21
ERC
of Expander. ( RC = 33 msec ) Pre - amp inverting input terminal of Expander. Adjusts the negative feedback loop gain. ( in application, gain is 5 ) Reference current input terminal of Automatic Level Control ( ALC) ; Adjusts THD of compressor output voltage to less than 3 % or limites the frequency deviation of TX if the input is higher than a certain level. The ALC circuit may be turned off depending on the ALC reference current or the magnitude of output voltage may be limited if it is higher than a certain level. ( Iref = 8uA, Ralc = 120K)
22
EPI -
23
ALC
KB8527B
1 CHIP CLP SUBSYSTEM IC
Pin No
Symbol
Description Reference voltage ( VREF= 1V ). Supplies a regulator voltage to the Compressor and Expander of COMPANDER. Output terminal of the Meter Driver.
24
VREF(COMP)
25
MDO
Amplitude of RF input signal for useful frequency is detected by Meter Driver circuit. The Meter Driver circuit has perfect linear characteristic of 60 dB range for input signal level. ( 0.1V / dB ) Output terminal of Data Slicing comparator.
26
DSCO
Seperates Frequency Shift Keying ( FSK ) serial data and executes data shapping and limiting.
27
DSCI
Input terminal of Data slicing comparator. Non - inverting type with the negative input terminal biased to 1/2 Vcc. Recovered Audio Output terminal. Voice signals detected by the Quadrature
28
RAO
Detector are amplified and then output through this terminal. Quadrature coil input terminal.
29
QCI
The 455 KHz oscillator circuit is an Lp=680uH, Cp=180pF valued LC tank circuit. Voice signals are detected by mixture of 455 KHz ( by phase difference ) which is converted from mixer 2. Ground . Ground for Receiver.
30
GNDRX
Limiter input and decoupling terminal. Removes amplitude modulation elements caused by fading or FM signal noise. 31 LD Limiting IF amplifies and limits the second intermediate frequency, 455 KHz. The input impedance of the limiting IF amplifier is set to 1.5 K . 32 LI While FM waves are transmitted with constant magnitude, their magnitudes are slightly modulated due to reflection from obstacles, fading phenomenon, noise wave, and mixing with AM wave elements before entering the receivers antenna. The limiter makes amplitude uniform by removing these AM wave elements.
KB8527B
1 CHIP CLP SUBSYSTEM IC
Pin No
Symbol
Description Supply voltage. Supplies power to the Receiver. Output terminal of Mixer 2. Second intermediate frequency ( 455 KHz ), generated by mixing first intermediate frequency ( 10.7 MHz ) and Second Local Oscillator is output. Input terminal of second local oscillator. Generates second local oscillator frequency to convert output from mixer 1 ( 10.7 MHz ) into second intermediate frequency. It is an oscillator with crystal of 10.24 MHz and 10.245 MHz. Input terminal of mixer 2. Output from mixer 1 is entered to mixer 2 input terminal
33
VCC(RX)
34
2MO
35 36
2LOI 2LOI
37
2MI
via 10.7 MHz ceramic filter. Second mixer converts frequency to second intermediate frequency ( 455 KHz : AM IF ). Output terminal of mixer 1. The signal from mixer 1 and the frequency of the first local oscillator are mixed
38
1MO
to produce the first intermediate frequency, which is the output through this terminal. The output terminal is an emitter follower with an output impedance of 330 to match the 330 input / output impedance of the 10.7 MHz ceramic filter.
Input terminal of the first local oscillator. 39 40 1LOI 1LOI The local oscillator is a voltage controlled oscillator. local oscillation frequency and received frequency are mixed at mixer 1 and then conerted to the first intermediate frequency of 10.7 MHz or 10.695 MHz.
The terminal which variable capacitor is included in the chip. Used as an input terminal where 1st local oscillation frequency is changed by varying the capacitor 41 VCORX connected between 1st local oscillator terminals. The internal variable capacitor has the value of 18.73 ~ 15.86 pF depending on the applied voltage. ( 1.0 ~ 2.0 V ) 42 43 1MI 1MI GND
(PLL)
Input terminal of Mixer 1. This mixer is made of double balanced multiplier. The received signal amplied at RF AMP is input to this teminal. Ground. Ground for analog at PLL.
44
KB8527B
1 CHIP CLP SUBSYSTEM IC
Pin No
Symbol
Description Phase detector output terminal of the receiver at PLL.
45
PDR
If fRX > fREF or fRX is Leading If fRX < fREF or fRX is Lagging If fRX = fREF and the same phase
The output is negative pulse The output is positive pulse The output is high impedance
PLL voltage reference output pin. 46 VREF(PLL) An internal voltage regulator provides a stable power supply voltage for the RX and TX PLLs.
47
VCC(PLL)
Power supply terminal of PLL.
Input terminal of TX channel counter. 48 TIF AC coupling with TX VCO. Minimum input level is 300 mVp-p ( at 60MHz ).
KB8527B
ABSOLUTE MAXIMUM RATINGS
Characteristic Maximum Supply Voltage Power Dissipation Operating Temperature Storage Temperature Symbol VCC PD TOPR TSTG
1 CHIP CLP SUBSYSTEM IC
Value 5.5 600 -20 ~ + 70 - 55 ~ + 150
Unit V mW
oC oC
CURRENT CONSUMPTION AT EACH MODE
( Vcc = 3.6V )
Modes Inactive mode RX mode Communication mode ( Active mode )
Min. -
Typ. 350uA 6.6mA 13.5mA
Max. 600uA -
CURRENT CONSUMPTION IN EACH BLOCK
( Vcc = 3.6V )
Modes Receiver part Expander part Speaker part compressor part PLL RX part TX part
Min. -
Typ. 5.0mA 1.4mA 1.7mA 3.0mA 1.6mA 0.8mA
Max. 7.5mA 2.1mA 2.5mA 4.5mA 2.4mA 1.2mA
KB8527B
ELECTRICAL CHARACTERISTICS
Characteristic Symbol
1 CHIP CLP SUBSYSTEM IC
Test Conditions
Min
Typ
Max
Unit
Operating Voltage
Vcc
2.0
-
5.5
V
RECEIVER
( VCC = 3.6V, fC = 49.7MHz, fDEV =+ 3KHz, fMOD = 1KHz,Ta = 25oC, unless otherwise specified ) Characteristic Input for -3dB Sensitivity Input for 20dB Sensitivity Symbol VLIM VI(SEN) S/N Test Conditions -3dB Point Modulation Input Modulation Input No Modulation Input RFin = 1mVrms Min Typ 0.7 0.7 Max 2.0 2.0 Unit Vrms Vrms
S/N Ratio
48
55
dB
Recovered Audio Output
VO(RA) VNO VO(RAD) VO(DET) VTH(DET) VTH VOH VOL GV(1M) GV(2M)
145
185
225
mVrms
Noise Output Level Recovered Audio Output Voltage Drop Detect Output Voltage Carrier Detector Threshold Comparator Threshold Voltage Difference Comparator Output Voltage 1 Comparator Output Voltage 2 First Mixer Conversion Voltage Gain Second Mixer Conversion Voltage Gain
RFin = No Input Vcc = 5V 2V RFin = 1mVrms RFin = 1mVrms
-
130
205
mVrms
-8
-3.3
-
dB
1.0
1.5
2.0
V
RFin = No Input VCOMP = 150mVp-p RL = 180K VCOMP = 150mVp-p RL = 180K VCOMP = 150mVp-p RL = 180K VI(43) = 1mVrms RL(38) = 330 VI(37) = 1mVrms RL(34) = 1.5K
0.49
0.60
0.73
V
70
110
150
mV
2.7
3.0
-
V
-
0.25
0.5
V
14
18
22
dB
17
21
25
dB
KB8527B
ELECTRICAL CHARACTERISTICS (Continued)
Characteristic Detector Output Distortion Detector Output Resistance Detector Output DC Voltage Change Ratio Meter Drive Slope First Mixer Input Resistance First Mixer Input Capacitance Limiter Input Sensitivity Second Mixer Input Sensitivity First Mixer 3rd Order Sensitivity Low Battery Detector Symbol THDDET RO(DET) VO(DET) MDS
1 CHIP CLP SUBSYSTEM IC
Test Conditions RFin = 1mVrms
Min -
Typ 1.5
Max 2.5
Unit %
RFin = 1mVrms
-
1.2
-
K
RFin = 1mVrms
70
0.15 100
0.23 135 -
V/KHz nA/dB
RI(1M) CI(1M) VI(LIM) SV(2M) 3RD
fc = 50MHz
500 -
690
fc = 50MHz fc = 455KHz, 20dB SINAD
7.2 100
10 250
pF V rms V rms
fc = 10.7MHz, 20dB SINAD
-
10
25
LBD0 ~ LBD3 Only LBD2 Only LBD1 Only LBD3 LBD0 ~ LBD3 = 0 ( Default ) =0 =0 =0 =1
-22 3.45 3.3 3.0 2.2 2.1 35
-
dBm
LBD
-0.15
0.1 0.075 -
V
- 0.1 25
AM Rejection Ratio
AMRR
RFin = 1mVrms ~ 10mVrms AM MOD = 30%
dB
Compressor
( Vcc = 3.6V, fc = 1KHz, Ta = 25oC, unless otherwise specified ) Characteristic Reference Voltage Standard Output Voltage Compressor Gain Difference Symbol VREF Vo(com) GV1(COM) GV2(COM) Test Conditions No Signal Vinc = 13mVrms Vinc = -20dB Vinc = -40dB 0dB Min 0.9 255 -1.0 -2.0 Typ 1.0 300 -0.5 -1.0 Max 1.1 345 0 0 Unit V mVrms dB dB
KB8527B
ELECTRICAL CHARACTERISTICS (Continued)
Characteristic Compressor Output Distortion Mute Attenuation Ratio Compressor Limiting Voltage ALC Splatter filter Symbol
1 CHIP CLP SUBSYSTEM IC
Test Conditions
Min 60
Typ
Max
Unit
THDCOM ATTMUTE VLIM(COM) VALC Vo(SF)
Vinc = 0dB Vinc = 0dB
0.5 80
1.0
% dB
Vinc = Variable IALC = 8uA ( RALC = 120K ) VINC = 13mVrms = 0 dB
1.41 280 255
1.65 330 300
1.83 380 345
Vp-p mVrms mVrms
Expander
(Vcc = 3.6V, fc = 1KHz, Ta = 25oC, unless otherwise specified) Characteristic Standard Output Voltage Symbol V O(EXP) GV1(EXP) Expander Gain Difference GV2(EXP) GV3(EXP) Expander Output Distortion Mute Attenuation Ratio Expander Maximum Output Voltage Speaker amp output 1 THDEXP ATTMUTE VOEXP(MAX) Vo( SA1) Test Conditions VinE = 30mVrms VinE = -10dB VinE = -20dB VinE = -30dB VinE = 0dB VinE = 0dB VinE = Variable THD = 10% VINE = 30mVrms = 0 dB 0dB Min 104 0 Typ 130 Max 156 Unit mVrms
0.5
1.0
dB
0
1.0
2.0 3.0
dB
0
1.5
dB
-
0.5
1.0
%
60
80
-
dB
500 104
600
-
mVrms
130
156
mVrms
Speaker amp output 2
Vo( SA1)
VINE = 30mVrms = 0 dB
104
130
156
mVrms
KB8527B
PLL
( Vcc = 3.6V, Ta = 25oC, unless otherwise specified ) Characteristic Symbol
1 CHIP CLP SUBSYSTEM IC
Test Conditions
Min
Typ
Max
Unit
Operating Current
ICCPLL IIH
Vcc = 3.6V
-
2.0 -
3.5
mA A A
Vin = Vcc
-
5 -
Input Current IIL VIH Input Voltage VIL IOH Output Current IOL VOH1 VOL1 Output Voltage VOH2 VOL2 PLL regulator voltage VPLLREG LD,fMCU : Io = -0.1mA ( Sourcing ) LD,fMCU : Io = 0.1mA ( Sinking ) Vcc0.5 V Vout = 0V PDT,PDR : Io = -0.3mA ( Sourcing ) PDT,PDR : Io = 0.3mA ( Sinking ) 0.3 Vcc0.4 mA Vout = Vcc Vin = 0V -5 Vcc0.3 -
-
-
V
-
0.3 -
V
0.3
-
mA
-
-
V
-
0.4
V
-
0.5 2.25
V
1.95
2.15
V
KB8527B
PLL Program summary
* MCU ( MICOM ) Serial Interface ( MSB : 1'st INPUT )
1 CHIP CLP SUBSYSTEM IC
Use CLK (Pin 7 ), DATA (Pin 8 ) , EN (Pin 9 ) terminals for program. DATA and CLK terminals are used for loading data to internal Shift - Register. When EN terminal is Low , It is possible to program TX-Channel Counter, RX - Channel Counter and various control functions of PLL. When EN terminal is High , Program 1st Local Oscillator Capacitor Selection in receiver for U.S.A - 25 CH function. - TX - Register, RX-Register, Control Register MSB DATA
PMC0 PMC1 14 Bit DATA
LSB
EN CLK
- Reference - Register MSB DATA
PMC0 PMC1 UK_S1 UK_S0 12 Bit DATA
LSB
EN CLK
- RECEIVER -1st local oscillator internal capacitor selection register & low battery detector voltage register [ CLO _ LBD - Register ] MSB DATA
PMC LBD3 LBD2 LBD1 LBD0 CLO5 CLO4 CLO3 CLO2 CLO1
LSB
CLO0
<1> EN CLK
KB8527B
* Programmable Counter
1 CHIP CLP SUBSYSTEM IC
- RX - counter : Setting frequency for RX.VCO ( 14 Bits --> 1/16 ~ 1/16383 ) [ Default_CH. = USA_#21 ( REMOTE ) : 36.075MHz ( Div._NO = 7215 )] < RX. Register (16bits) > Bit Name Default value 7215 Bit 15 PMC0 * Bit 14 PMC1 Bit 13 D13 0 Bit 12 D12 1 Bit 11 D11 1 Bit 10 D10 1 Bit 9 D9 0 Bit 8 D8 0
Bit Name Default value 7215
Bit 7 D7 0
Bit 6 D6 0
Bit 5 D5 1
Bit 4 D4 0
Bit 3 D3 1
Bit 2 D2 1
Bit 1 D1 1
Bit 0 D0 1
- TX - counter : Setting frequency for TX.VCO ( 14 Bits --> 1/16 ~ 1/16383 ) [ Default_CH. = USA_#21 ( REMOTE ) : 49.830MHz ( Div._NO = 9966 )]
< TX. Register (16 bits) > Bit Name Default value 9966 Bit 15 PMC0 * Bit 14 PMC1 Bit 13 D13 1 Bit 12 D12 0 Bit 11 D11 0 Bit 10 D10 1 Bit 9 D9 1 Bit 8 D8 0
Bit Name Default value 9966
Bit 7 D7 1
Bit 6 D6 1
Bit 5 D5 1
Bit 4 D4 0
Bit 3 D3 1
Bit 2 D2 1
Bit 1 D1 1
Bit 0 D0 0
* Program mode control
PMC0 0 1 PMC1 0 0 Program mode Control Block UPLL_Ref. Block PMC0 0 1 PMC1 1 1 Program mode UPLL_RX. Block UPLL_TX. Block
KB8527B
1 CHIP CLP SUBSYSTEM IC
- Ref - counter : Setting reference frequency for phase detector ( 12 Bits --> 1/16 ~ 1/4095 ) [ Default_Divider = 2048, X-tal_OSC = 10.240 MHz -->Fref = 5KHz ] < Ref. Register (16bits) > Bit Name Default value 2048 Bit 15 PMC0 * Bit 14 PMC1 Bit 13 UK_S1 Bit 12 UK_S0 Bit 11 D11 1 Bit 10 D10 0 Bit 9 D9 0 Bit 8 D8 0
Ref.freq. selection for United Kingdom
Bit Name Default value 2048 -UK_Selection
UK_S0 0 1 0 1
Bit 7 D7 0
Bit 6 D6 0
Bit 5 D5 0
Bit 4 D4 0
Bit 3 D3 0
Bit 2 D2 0
Bit 1 D1 0
Bit 0 D0 0
UK_S1 0 0 1 1
FR1 fREF (A) fREF (A) fREF/4 (B) fREF/4 (B)
FR2 fREF/4 (B) fREF/25 (C) fREF/25 (C)
FrefTX fREF (A) fREF/4 (B) fREF/4 (B) fREF/25 (C)
FrefRX fREF (A) fREF/4 (B) fREF/25 (C) fREF/4 (B)
fREF (A) 12 Bits Reference program divider. FR1
LD
. .
4
fREF (B)
.4 . .
FR2
PD_TX
. 25 .
fREF . 25 (C)
PDT PDR
PD_RX
< Reference frequency selection >
KB8527B
* Control program Control register (16 Bits) Bit Name Description Bit 15 PMC0
Program Mode Control_0
1 CHIP CLP SUBSYSTEM IC
Bit 14 PMC1
Program Mode Control_1
Bit 13 Dont Care
Bit 12
PLLTX-BS PLL_Tx Battery Save 0:Normal (PLL_TX-On) 1:PLL_TX Power-Off
Bit 11 CO_M
Compressor Mute Selection
Bit 10 CO_BS
Compressor Battery Save 0: CO-On 1: Normal ( CO-part Power-Off )
Bit 9 EX_M
Expander Mute Selection
Bit 8 EX_BS
Expander Battery Save 0: EX-On 1: Normal ( EX-part Power-Off )
Function
* Program Latch Assign
Dont Care
0:Normal 1:Mute
0:Normal 1:Mute
Bit Name Description
Bit 7
Bit 6
Bit 5 Rx-BS
RX Battery Save
Bit 4 Dont care
Bit 3 Dont care
Bit 2 Dont care
Bit 1 TEST2
TEST Mode 2
Bit 0 TEST1
TEST Mode 1
LDT_CDO LBD-BS
LDT or CDO Select Low Battery Detector Battery Save 0:Normal (LBD-ON) 1:LBD-Part Power-Off
Function
0:Normal (CDO) 1:LDT
0:Normal (RX-ON) 1:RX-Part Power-Off
-
*** Function Test On each block of UPLL
*** TEST Mode & LDT-CDO Mode LDT/CDO TEST1 0 0 1 0 1 0 1 1 0 1 TEST2 0 0 1 1 0 0 1 1 LDT / CDO Rx block CDO Rx block CDO 4_25cnt block FR2 4_25cnt block FR2 PLL block LDT PLL block LDT Test PLL_RX Test PLL_TX Remark Default
KB8527B
* Operating internal circuit blocks in each mode Mode ( state )
1 CHIP CLP SUBSYSTEM IC
Operating circuit blocks
Active state ( Communication mode )
PLL regulator / MICOM I/F ( Data, CLK, EN ) / 2nd local oscillator / Receiver / 1st local oscillator / RX PLL / Carrier detector / FSK comparator / Low battery detector / TX PLL / Expander & speaker amp / Compressor / Splatter filter amp PLL regulator / MICOM I/F ( Data, CLK, EN ) / 2nd local oscillator / Receiver / 1st local oscillator / RX PLL / Carrier detector / FSK comparator / Low battery detector.
Receiving mode
Inactive state
PLL regulator / MICOM I/F ( Data, CLK, EN )
* CLO_LBD - Register Program [ Rx - 1st local oscillation internal cap. for U.S.A - 25CH & Low battery detect voltage ] - CLO register ( 6 bits ) : Receiver 1st local oscillator internal capacitor selection Bit Name
Default Value 0
Bit10 (MSB) PMC
Bit 5 CLO5
Bit 4 CLO4
Bit 3 CLO3
Bit 2 CLO2
Bit 1 CLO1
Bit 0 CLO0
1 *****
-
0
0:Normal 1:Internal Cap. for USA 25 Channel =4.4pF
0
0:Normal 1:Internal Cap. for USA 25 Channel =1.0pF
0
0:Normal 1:Internal Cap. for USA 25 Channel =3.6pF
0
0:Normal 1:Internal Cap. for USA 25 Channel =2.4pF
0
0:Normal 1:Internal Cap. for USA 25 Channel =1.2pF
0
0:Normal 1:Internal Cap. for USA 25 Channel =0.6pF
Function
***** PMC ( Program Mode Control ) PMC = HIGH & EN = HIGH ---> CLO_LBD Register Program Mode
KB8527B
1 CHIP CLP SUBSYSTEM IC
- Rx - Low Battery Detect Voltage Bit 10 (MSB) PMC Low Battery Detector Voltage
Bit Name Default Value
Bit 9 LBD3
Bit 8 LBD2
Bit 7 LBD1
Bit 6 LBD0
Remark
1 *****
0
0 1
0
0 0 1 1 1
0
0 1 0 1 1
0
0 1 1 1 1
3.45V 3.3V 3.0V 2.2V 2.1V
Default -
Function
1
1 0 1
***** PMC ( Program Mode Control ) PMC = HIGH & EN = HIGH ---> CLO - LBD Register Program Mode
* Example 1 > Low battery detector voltage : 2.1V U.S.A _CH-#1 ( REMOTE ) ---> 1st local osc. varicap value =15.86pF, Internal cap = 7.0pF ( Ext_L = 0.45uH, EXT_C = 30pF ) - 12 bit data format MSB Dummy
PMC bit 1( 0 ) LBD3 LBD2 1 1
LSB
LBD1 LBD0 CLO5 CLO4 CLO3 CLO2 CLO1 CLO0 1 1 0 1 1 1 0 0
DATA
1
EN CLK
In case the 12 bits programming, insert 1 dont care bit ( Dummy bit ) between PMC and LBD3.
KB8527B
1 CHIP CLP SUBSYSTEM IC
- In case of setting 16 bit data format
MSB
PMC
Dummy bit
LSB
LBD3 LBD2 LBD1 LBD0 CLO5 CLO4 CLO3 CLO2 CLO1 CLO0
DATA
1
1(0)
1(0)
1(0)
1(0)
1(0)
1
1
1
1
0
1
1
1
0
0
EN CLK
In case of 16 bits programming, insert 5 dont care bits between the PMC and LBD3
* EXAMPLE DATA FOR U.S.A 25_CHANNEL SELECTION
Base Channels Hand Channels 1 ~ 25CH. 16 ~ 25CH. 01 ~ 06CH. 07 ~ 15CH. Varicap Value 1.0V ~ 2.0V TYP 1.5V 18.73 ~ 15.86pF 18.73 ~ 15.86pF 18.73 ~ 15.86pF 18.73 ~ 15.86pF 18.73 ~ 15.86pF 18.73 ~ 15.86pF 18.73 ~ 15.86pF External C 27pF ( 30pF ) 27pF 30pF 27pF 27pF 27pF 30pF 30pF External L 0.45uH 0.45uH 0.45uH 0.45uH 0.45uH 0.45uH 0.45uH 0.45uH Internal C pF
1st Local Osc. Internal Capacitor Select
Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 ~ 25CH. (CLO5) (CLO4) (CLO3) (CLO2) (CLO1) (CLO0)
0 0 0 0 0 0 0
0 0 1 0 0 1 1
0 0 0 0 0 1 1
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 1 1 0 1 0 0
16 ~ 25CH. 01 ~ 04CH. 05 ~ 10CH. 11 ~ 15CH -
0.6 1.6 1.2 0.6 7.0 5.8
KB8527B
* Phase detector / Lock Detector Output Waveforms
1 CHIP CLP SUBSYSTEM IC
fREF (A) 12 Bits Reference program divider. FR1
LD
REF.Freq
. .
4
fREF . 4 (B) FR2
.
2LOI
. 25 .
14 Bits TX. program divider.
. fREF . 25
(C)
TIF
.N .
PD_TX
PDT
TIF
REF.Freq.
. TIF . N
PDT
LD
( Phase Detector / Lock Detector Output Waveform )

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